Engraving in 3 nm then 2 nm: TSMC’s future progress that will benefit Apple

Its progress, the new M2 chip owes it in part to an evolution of its engraving technology. Like the M1, it is engraved in 5 nm, but for it it is a second generation 5 nm engraving process, which is improved. TSMC, which produces the chips designed by Apple, does not intend to stop there.

At his Technology Symposium, the industry’s most important founder unveiled his roadmap for the next few years. As manufacturing processes become more and more complex, the gap between two levels will increase. It takes about two and a half years to switch from 5 nm to 3 nm engraving, then three years to start 2 nm engraving. TSMC is not going to sit idly by during this time: as it currently does with the second generation 5nm, there will be insufficient optimizations at 3nm before 2nm emerges.

Mass etching in 3 nm, named N3 in its first version, will begin in the second half. In time for the iPhone 14 Pro’s A16 chip then? Maybe not. As a previous analyze pointed out, the Hourly might be too fair. TSMC communicates on 3 nm chips integrated into the final products at the beginning of 2023. The A16 could be satisfied with 5 nm, or even 4 nm (N4P). Either way, if Apple doesn’t take advantage of 3nm for the A16, it will take advantage of it for a future chip.

Compared to the first generation 5 nm engraving (A14, A15 and M1 chips), the N3 should bring a performance gain of 10 to 15% at equal consumption or a reduction in consumption of 25 to 30% at equal performance . The logic density will be reduced by 42%, which means that more transistors could be packed into the same space. TSMC will then optimize this with the N3E, N3P, N3S and N3X processes from 2023 until 2025.

An important aspect of the N3 nodes will be the new FinFlex technology. To sum up very briefly, this technology will allow designers of personalization chips more to develop their architecture in order to adapt power, consumption and surface very precisely.

After the N3 will come the N2. Compared to the N3E (this is the point of comparison given by TSMC), this first 2 nm engraving node promises a performance gain of 10 to 15% at equal consumption, or a reduction in consumption of 25 to 30% at equal performance. The first products integrating chips engraved in 2 nm are planned for the second half of 2025.

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